1. Field of the Invention
This invention concerns a control signal output circuit for a semiconductor device, and more particularly a control signal output circuit for a semiconductor memory circuit.
2. Description of the Prior Art
Conventionally, positive and negative logic control signals are used to increase the degree of freedom of control when producing a control signal for a semiconductor device, such as a semiconductor memory device.
FIG. 1 shows a block diagram of a semiconductor memory device in which positive and negative logic control signals CE1, CE2 are used to produce a chip control signal CE.
In this device, when the signal is low level and the CE2 signal is high level, the internal components of the chip are activated and the semiconductor memory device performs its normal operation. Namely, an address signal A is input to an address input circuit 2, and a corresponding memory cell in a memory cell array 4 is selected in accordance with the address signal supplied via a row decoder 3 and a column decoder 5 (including a sense amplifier circuit and a write circuit).
In the read operation, a read/write control signal R/W is supplied via a read/write control circuit 6 to control a data input/output circuit 7 so as to output a data from an I/O terminal.
In the write operation, the R/W signal controls the data input/output circuit 7 and a write circuit (included in block 5) to write data input to the input output terminal I/O into a corresponding memory cell in the memory cell array 4 in accordance with an address signal from the address input circuit 2.
FIG. 2 shows a circuit diagram of a conventional chip control circuit 1 in FIG. 1. The control circuit of FIG. 2 includes an inverter circuit 11 and a NOR circuit 12. A positive logic control signal CE2 is inverted by the inverter circuit 11 and supplied to the NOR circuit 12. The NOR circuit 12 produces a chip control signal CE in response to the output signal of the inverter 11 and a negative logic control signal CE1.
FIG. 3 shows a circuit diagram of another conventional chip control circuit. The circuit of FIG. 3 includes an inverter circuit 13, a NAND circuit 14 and an inverter circuit 15. A negative logic control signal CE1 is inverted by the inverter circuit 13 and supplied to the NAND circuit 14. The NAND circuit 14 and the inverter circuit 15 produces a chip control signal CE in response to the output signal of the inverter 13 and a positive logic control signal CE2.
In these circuits, the chip control circuit 1 produces a high level CE signal only when the negative logic control signal CE1 is low level and the positive logic control signal CE2 is high level, and the internal components of the chip are activated to perform the predescribed normal operation. When the negative logic control signal CE1 is high level or the positive logic control signal CE2 is low level, the chip control signal CE changes to low level, and the internal components of the semiconductor memory are changed into a disabled state. In this way, using the positive and the negative logic control signals to produce a control signal, the degree of freedom of the semiconductor device is increased as the disabled state of the semiconductor device is achieved by controlling one of the positive and the negative logic signals
In the disabled state, the semiconductor device assumes a stand-by state and a reduction of the power consumption is achieved. Particularly when complementary MOS (CMOS) circuits are used, the consumption current can be reduced to a leak current. For example the leak is only about several .mu.As in the case of a 64K bit CMOS static RAM.
However in the conventional circuit of FIG. 2, a relatively large current flows through the inverter circuit 11 according to the level of the CE2 signal. Namely, in the case where a CMOS type inverter circuit is used for the inverter circuit 11, a relatively large current flows through the inverter circuit when the CE2 signal changes. Especially, in the case where the CE2 signal is at an intermediate level, a kind of DC current of several mA flows. The amount of this current can be as large as about 1000 times the magnitude of the leak current.
In the case where an N channel type MOS transistor having a load is used for the inverter circuit 11, a relatively large current flows through the inverter when the CE2 signal is high level.
Thus, the total power consumption, including these currents, increases even if the CE signal is low to achieve the stand-by state for reducing the power consumption.
In the conventional circuit of FIG. 3, a relatively large current also flows through the inverter 13.
To prevent this current from flowing through the inverters 11 and 13, it is necessary to make the CE2 signal low level in the circuit of FIG. 2, and to make the CE1 signal high level to achieve a CE signal of low level and produce the stand-by state. This is a restriction of the system, and the merit of using the two signals CE1 and CE2 is lost.